2-3 Performance of ICT / ICL 1900 Series (All Models) and derivatives 2903/ME29    (by Virgilio Pasquali)

 

In a compatible range, addressing a wide and continuous span of the market, it became increasingly important to position each model in the range relative to the other models.

Careful spacing of processors performance in the range ensured coverage of the market span with the minimum of models, without leaving significant gaps, with the resulting savings in development costs, production and sales costs.

The need to specify and measure processor performance in a more meaningful way led to the definition of “Work mixes”, representative loops of instruction that could be coded and run meaningfully on all machines.

Amongst the most widely used mixes were POWU2, GAMM, Gibson, Knuth (Fortran) and Wichmann (Algol).

 

ICT used extensively POWU2 as a performance measurement of “commercial” data processing (without Floating Point instructions) and GAMM mix for “scientific” computing (dominated by Floating Point instructions).

POWU2 was of particular importance. Specified by the UK Post Office (Post Office Work Unit2), it was used to specify performance in UK government purchases.

 

In ICT (and later ICL) it was used in the specification of product requirements, in the measurement of the performance of competitive systems and in the setting of system prices in the market (in general, 1900 prices were set at 5% below the IBM360 (later IBM370) price performance curve).

 

The following is an extract from an ICL document on performance (dated 1972):

 

 e) On some machines it is possible to code the POWU 2 in various ways, each producing different results.  The figures quoted for such machines are not necessarily the optimum obtainable within the POWU 2 definition but are intended to be realistic in terms of actual processing.         

 

 f)  The instruction sets of different ranges of machines (within ICL and competition) are not identical and the number of instructions required to code POWU 2 accordingly varies from one machine to another.  On 1900 there are 880 instructions in the loop.

 g) For multi-processor configurations each processor can be rated separately but no general statement can be made to represent the power of a total system without reference to specific workloads.

 

 Some manufacturers quote the instruction processing rate of their CPUs. In some cases, however, this is the rate of processing the shortest instructions and not the average of a typical instruction mix.

 

 

 

 

Original 1900 Series

 

The following table was measured in term of POWU 2 and GAMM after first deliveries and it is included for completeness.

 

System

First Delivery

Performance

Clock nS

POWU 2 ms.

POWU 2/Sec

GAMM uS

1907 (1Us)

 

1967

 

4

268

12

750

1906 1us

 

1967

 

4

268

 

750

1907 (2us)

 

1967

 

5

200

14

750

1906 2us

 

1967

 

5

200

 

750

1909

 

Aug-65

 

7.5

133

29

 

1905

 

May-65

 

8

133

29

1000

1904

 

1965

 

7.5

133

 

1000

1903

 

1965

 

18

55

 

1000

1903 EMU

 

 

 

16

64

86

1000

1902

 

1965

 

45

22

 

 

1902 EMU *

 

 

 

40

25

116

 

1901

 

Mar-66

 

83

12

 

4000

1901 EMU *

 

1966

 

67

15

130

4000

*EMU = Extended Mathematical Unit

The E/F’s

 

The E/F series used the same hardware technology as the original 1900, but included significant optimisation of the design and significant enhancements of the 1900 architecture.

The resulting improvement of the performance should be noticed (a single 1904/5 F almost reaches the performance of the original 1906/7).

The raw computing power available in an anonymous dual processor system (1906/7E/F) was measured at 1.8 times a single.

The following table was measured in term of POWU 2 and GAMM after first deliveries and it is included for completeness.

 

 

System

First Delivery

Performance

Clock nS

 

 

POWU 2 ms.

POWU 2/Sec

GAMM uS

1907 E/F

 

1968

 

1.8x1905 E/F

750

1906 E/F

 

1968

 

1.8x1904 E/F

750

1905E

 

1967

 

6

158

29

750

1905E (H/W Registers)

1967

 

5

189

28

750

1905F

 

1967

 

4.3

233

18

750

1904E

 

1967

 

6.3

158

 

750

1904E (H/W Registers)

1967

 

5.3

189

 

750

1904F

 

1967

 

4.3

233

 

750


 

The 1900 A Series

Having achieved a well understood and stable architecture, ICT applied state of the art integrated circuit technology and the necessary advanced packaging technology, with significant improvements in the competitiveness of the 1900 range.

 

System

First Delivery

Performance

Clock nS

 

 

POWU 2 ms.

POWU 2/Sec

GAMM uS

1906A

 

1970

 

0.9

1111

 

100

1904A

 

1969

 

3

333

11

500

1903A

 

1968

 

5.8

172

 

720

1903A SCF†

 

1968

 

5.8

172

44

720

1902A

 

1968

 

21

47

 

1500

1902A CCF‡/SCF†

1968

 

11

87

87

1500

1901A

 

1969

 

63

16

 

 

1901A CCF‡

 

1969

 

45

22

109

 

‡ CCF= Commercial Computing Feature (Group 4 instructions- Fixed Point Multiply/Divide and I/O conversion)

†SCF= Scientific Computing Feature (Group 13 FP instructions – held FP Accumulator)

 


The 1900 S series and 1900 T’s

 

The 1900 S series, the last to span the whole range, was mainly an evolutionary enhancement, achieved by selectively applying faster technologies to the 1900A designs. This development achieved very significant performance improvements with relatively modest development resources.

 

The 1900 T models, introduced in the lower part of the range. were mainly a re-badging (and cost reduction) exercise. Performance and specification improvements for each model were achieved mainly by regrading the higher model.

 

System

First Delivery

Performance

Clock nS

 

 

POWU 2 ms.

POWU 2/Sec

GAMM uS

1906S

 

1973

 

0.65

1540

 

100

1904S

 

1972

 

2.3

435

10.5

300

1903S

 

1971

 

5.8

172

44

640

1903T

 

1973

 

4

250

15

 

1902S

 

1971

 

11

87

87

1500

1902T

 

1974

 

7

152

55

1000

1901S

 

 

 

50

20

 

 

1901S CCF‡

 

 

 

31

32

90

 

1901T

 

1974

 

13

76

95

 

 

 

The 2903 and ME29

 

The 2903 series, an innovative design still using 1900 order code, was introduced shortly before the announcement of the 2900 mainframes models (hence the name and its “tango” skin).

It was competing well in the “low cost” computing market. Addressed to small companies without a DP department, ease of use was more important than the raw performance of its processor.

 

System

First Delivery

Performance

Clock nS

 

 

 

 

POWU 2 ms.

POWU 2/Sec

GAMM uS

2903/25

 

May-76

 

23

44

 

540

2903/40

 

May-74

 

17

60

 

540

2904

 

May-76

 

9

111

 

540

ME29

 

1980

 

7

150